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NXP Semiconductors /LPC11E6x /DMATRIGMUX /DMA_ITRIG_PINMUX[7]

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Interpret as DMA_ITRIG_PINMUX[7]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INP_N0RESERVED

Description

Trigger input select register for DMA channel 0.

Fields

INP_N

Trigger input number (decimal value) to DMA channel n. All other values are reserved. 0 = ADC0_SEQA_IRQ 1 = ADC0_SEQB_IRQ 2 = CT16B0_MAT0 3 = CT16B1_MAT0 4 = CT32B0_MAT0 5 = CT16B1_MAT0 6 = PINT0 ( pin interrupt 0) 7 = PINT1 (pin interrupt1 ) 8 = SCT0_DMA0 9 = SCT0_DMA1 10 = SCT1_DMA0 11 = SCT1_DMA1
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data